Integral INSSD64GP25MXZ Ficha Técnica descarregar pdf (Página 14)

Multiword DMA timing parameters

Mode

0 ns

Mode

1 ns

Mode

2 ns

Note

Cycle time

(min)

480

150

120

See

note

DIOR-/DIOW- asserted pulse width

(min)

215

See

note

DIOR- data access

(max)

150

DIOR- data hold

(min)

DIOR-/DIOW- data setup

(min)

100

DIOW- data hold

(min)

DMACK to DIOR-/DIOW- setup

(min)

DIOR-/DIOW- to DMACK hold

(min)

DIOR- negated pulse width

(min)

See

note

DIOW- negated pulse width

(min)

215

See

note

DIOR- to DMACK delay

(max)

120

DIOW- to DMACK delay

(max)

CS(1:0) valid to DIOR-/DIOW-

(min)

CS(1:0) hold

(min)

DMACK- to read data released

(max)

Notes- t

is the minimum total cycle. t

is the minimum DIOR-/DIOW- assertion time,

and t

or t

, as appropriate) is the minimum DIOR-/DIOW- negation time. A host

shall lengthen t

and/or t

to ensure that t

is equal to the value reported in the

devices IDENTIFY DEVICE data.

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